With ATtiny2313 it is possible to utilize two 16-bit PWM using OC1A and OC1B.
If application needs more than this, say RGB controller, two additional 16-bit channels can be created from native 8-bit OC0A and OC0B. The resolution is true 16-bit, glitch-free. Prescaler can be set to 1.
The software emulated PWM behaves as its hardware counterpart, except that its registers are in data SRAM, here called RegOCR0AL and RegOCR0AH.
A small limitation is that duty cycle can not be too small. The value of RegOCR0AH:RegOCR0AL must be limited to, say FF80h (inverted PWM) depending on particular program environment.

In this assembler code example are shown only essential parts of software PWM implementation. The goal is to supply the basic idea of how to create 16-bit PWM using 8-bit OC and 16-bit timer, in this case OC0A and TCNT1.
Other parts such as initialization and main program are not shown because they are application specific.

;****************************************************************

; ****    CONSTANTS

;****************************************************************

.equ    TCCR0A_Set_OC_Val    = (1<<COM0A1) | (1<<COM0A0)

.equ    TCCR0A_Clear_OC_Val  = (1<<COM0A1) | (0<<COM0A0)

;****************************************************************

; ****    GLOBAL VARIABLES

;****************************************************************

.dseg

RegOCR0AL:            .byte    1

RegOCR0AH:            .byte    1

;****************************************************************

; ****    INTERRUPT VECTORS

;****************************************************************

.cseg

.org    $0000

    rjmp    Reset                ; Reset handler                     $0000

    rjmp    INT0_Int_Entry       ; External Interrupt0               $0001

    rjmp    INT1_Int_Entry       ; External Interrupt1               $0002

    rjmp    ICP1_Int_Entry       ; Input capture interrupt 1         $0003

    rjmp    OC1A_Int_Entry       ; Timer/Counter1 Compare Match A    $0004

    rjmp    OVF1_Int_Entry       ; Overflow1 Interrupt               $0005

    rjmp    OVF0_Int_Entry       ; Overflow0 Interrupt               $0006

    rjmp    URXC0_Int_Entry      ; USART0 RX Complete Interrupt      $0007

    rjmp    UDRE0_Int_Entry      ; USART0 Data Register Empty        $0008

    rjmp    UTXC0_Int_Entry      ; USART0 TX Complete Interrupt      $0009

    rjmp    ACI_Int_Entry        ; Analog Comparator Interrupt       $000A

    rjmp    PCINT_Int_Entry      ; Pin Change Interrupt              $000B

    rjmp    OC1B_Int_Entry       ; Timer/Counter1 Compare Match B    $000C

    rjmp    OC0A_Int_Entry       ; Timer/Counter0 Compare Match A    $000D

    rjmp    OC0B_Int_Entry       ; Timer/Counter0 Compare Match B    $000E

    rjmp    USI_START_Int_Entry  ; USI start interrupt               $000F

    rjmp    USI_OVF_Int_Entry    ; USI overflow interrupt            $0010

    rjmp    ERDY_Int_Entry       ; EEPROM write complete             $0011

    rjmp    WDT_Int_Entry        ; Watchdog Timer Interrupt          $0012

;****************************************************************

; ****    INTERRUPT ENTRY

;****************************************************************

.cseg

OC0A_Int_Entry:

    push    zl

    in      zl, SREG

    push    zl

    push    zh

    push    yl

    push    yh

;-------------------------------

    lds     yl, RegOCR0AL            ; OCR low byte

    lds     yh, RegOCR0AH            ; OCR hihg byte

    in      zl, TCNT1L               ; timer low byte

    in      zh, TCNT1H               ; timer high byte

    cpi     zh, $FF                  ; top value

    breq    _FF_Clear

    sub     zl, yl

    sbc     zh, yh

    brcc    RegOCR0AL_Set

    cpi     zh, $FE

    breq    Wait_a_little            ; FE, <= 200h MCU cycles

    brcc    RegOCR0AL_Set            ; FF, <= 100h MCU cycles

    rjmp    RegOCR0AL_Clear          ; > 200h MCU cycles

Wait_a_little:

    cpi     zl, $E0

    brcs    RegOCR0AL_Clear          ; too many MCU cycles, don't wait

    in      zl, TCNT0

    cp      zl, yl                   ; RegTCNT0L, RegOCR0AL

    brcs    PC - 2

    rjmp    RegOCR0AL_Set            ; < 100h MCU cycles now

_FF_Clear:

    out     OCR0A, zh

    ldi     zl, TCCR0A_Clear_OC_Val

    out     TCCR0A, zl               ; clear output on compare

    rjmp    Leave_OC0A_Int

RegOCR0AL_Set:

    out     OCR0A, yl

    ldi     zl, TCCR0A_Set_OC_Val

    out     TCCR0A, zl               ; set output on compare

    rjmp    Leave_OC0A_Int

RegOCR0AL_Clear:

    out     OCR0A, yl

    ldi     zl, TCCR0A_Clear_OC_Val

    out     TCCR0A, zl               ; clear output on compare

    rjmp    Leave_OC0A_Int

;------------------------------

Leave_OC0A_Int:

    pop     yh

    pop     yl

    pop     zh

    pop     zl

    out     SREG, zl

    pop     zl

    reti

; Bit definitions

#define    _c      status,0

#define    _z      status,2

#define    _dc     status,1

#define    _gie    intcon, 7

; Macro definitions

Bank1    macro

    bsf    status, 5

    endm

Bank0    macro

    bcf    status, 5

    endm

; Mov pointer Work register with Literal

MovWL    macro    Literal

    movwf    fsr

    movlw    low(Literal)

    movwf    indf

    incf     fsr

    movlw    high(Literal)

    movwf    indf

    endm

; Mov File register from Literal

MovFL    macro    File, Literal

    movlw    low(Literal)

    movwf    File

    movlw    high(Literal)

    movwf    File + 1

    endm

; Compare Literal with File register

CmpLF    macro    Literal, File

    movf     File + 1, w

    sublw    high(Literal)

    btfss    _z

    goto     $ + 3

    movf     File,  w

    sublw    low(Literal)

    endm

; Compare File register with Literal

CmpFL    macro    File, Literal

    movlw    high(Literal)

    subwf    File + 1, w

    btfss    _z

    goto     $ + 3

    movlw    low(Literal)

    subwf    File, w

    endm

; Compare File register Destination with File register Source

CmpFF    macro    FileD, FileS

    movf     FileS + 1, w

    subwf    FileD + 1, w

    skpz

    goto     $ + 3

    movf     FileS,  w

    subwf    FileD, w

    endm

; Add File register Source to File register Destination

AddFF    macro    FileD, FileS

    movf     FileS, w

    addwf    FileD,F

    skpnc

    incf     FileD + 1

    movf     FileS + 1, w

    addwf    FileD + 1

    endm

; Data declarations

     cblock    0ch

AccA    :2

AccB    :2

W1

Flags   :1

    endc

;  Routines

; Mov accumulator A from pointer Work register

MovAW

    movwf    fsr

    movf     indf, w

    movwf    AccA

    incf     fsr

    movf     indf, w

    movwf    AccA + 1

    return

; Mov pointer Work register from accumulator A

MovWA

    movwf    fsr

    movf     AccA, w

    movwf    indf

    incf     fsr

    movf     AccA + 1, w

    movwf    indf

    return

; Increment pointer Work register

IncW

    movwf    fsr

    incfsz   indf

    return

    incf     fsr

    incf     indf

    return

; Decrement pointer Work register

DecW

    movwf    fsr

    movlw    0ffh

    addwf    indf

    btfsc    _c

    return

    incf     fsr

    decf     indf

    return

; Compare accumulator A with pointer Work register

CmpAW

    movwf    fsr

    incf     fsr

    movf     indf, w

    subwf    AccA + 1, w

    btfss    _z

    return

    decf     fsr

    movf     indf, w

    subwf    AccA, w

    return

; Compare pointer Work register with accumulator A

CmpWA

    movwf    fsr

    incf     fsr

    movf     AccA  + 1, w

    subwf    indf, w

    btfss    _z

    return

    decf     fsr

    movf     AccA, w

    subwf    indf, w

    return

; Add pointer Work register to accumulator A

AddAW

    movwf    fsr

    movf     indf, w

    addwf    AccA

    btfsc    _c

    incf     AccA + 1

    incf     fsr

    movf     indf, w

    addwf    AccA + 1

    return

; Subtract pointer Work register from accumulator A

SubAW

    movwf    fsr

    movf     indf, w

    subwf    AccA

    btfss    _c

    decf     AccA + 1

    incf     fsr

    movf     indf, w

    subwf    AccA + 1

    return

; Subtract accumulator A from pointer Work register

SubWA

    movwf    fsr

    movf     AccA, w

    subwf    indf

    incf     fsr

    btfss    _c

    decf     indf

    movf     AccA + 1, w

    subwf    indf

    return

IncBCD

; Input:  AccB        Base  address

;         AccB + 1    Index

; Output: None

    movf      fsr, w        ; Store FSR

    movwf     w1

    bcf      _c

    rrf      AccB + 1, w    ; Get address

    addwf    AccB, w

    movwf    fsr

    btfsc    AccB + 1, 0

    swapf    indf

    movlw    9

    subwf    indf

    movlw    10

    btfss    _dc

    addwf    indf

    btfsc    AccB + 1, 0

    swapf    indf

    movf     w1, w          ; Restore FSR

    movwf    fsr

    return

Mul_8

; Input:  AccA           Multiplicand

;         AccB           Multiplicator

; Output: AccA+1:AccA    Result

    clrf     W1

    bsf      W1, 3

    clrf     AccA + 1

    movf     AccB, w

    rrf      AccA

Mul_SL0001

    btfsc    _c

    addwf    AccA + 1

    rrf      AccA + 1

    rrf      AccA

    decfsz   W1

    goto     Mul_SL0001

    return

Div_8

; Input:  AccA        Dividend

;         AccB        Divisor

; Output: AccA        Result

;         AccA+1      Remainder

    movlw    8

FDiv_Byte

    movwf    W1

    clrf     AccA + 1

Div_SL0001

    rlf      AccA

    rlf      AccA + 1

    movf     AccB, w

    subwf    AccA + 1, w

    btfsc    _c

    movwf    AccA + 1

    decfsz   W1

    goto     Div_SL0001

    rlf      AccA

    return

FDiv_8

    movlw    16

    goto     FDiv_Byte

Div_16_8

; Input:  AccA+1:AccA    Dividend

;         AccB           Divisor

; Output: AccA+1:AccA    Result

;         AccB+1         Remainder

    clrf     W1

    bsf      W1, 4

    clrf     AccB + 1

Div_SL0002

    rlf      AccA

    rlf      AccA + 1

    rlf      AccB + 1

    movf     AccB, w

    subwf    AccB + 1, w

    btfsc    _c

    movwf    AccB + 1

    decfsz   W1

    goto     Div_SL0002

    rlf      AccA

    rlf      AccA + 1

    return

Content of .asm file

; ***************************************************************

; This collection of routines allows an 80x51 microcontroller

; to read and write the I2C devices

; FOSC = 24MHz.

; ***************************************************************

_R         EQU        0

SDA        EQU        P3.1

SCL        EQU        P3.7

        RSEG RCODE

PUBLIC    I2C_Start

; void I2C_Start (void);

; Send START, defined as high-to-low SDA with SCL high

; Input:  None

; Output: None

; Registers destroyed: A, PSW, R1

I2C_Start:

        setb    SDA

        mov     A, #5          ; wait Tr + Tsu:dat, prevent "STOP"

        mov     R1, #7

        setb    SCL            ; release bus

        djnz    R1, $          ; wait Tr + Tsu:sta (> 5.7us)

        clr     SDA            ; high-to-low SDA with SCL high

        mov     R1, A

        djnz    R1, $          ; wait Tf + Thd:sta (> 4.3us)

        clr     SCL            ; SCL low, enable data change

        djnz    ACC, $         ; wait Tf + Tlow (> 5us)

        ret

PUBLIC    I2C_Stop

; void I2C_Stop (void);

; Send STOP, defined as low-to-high SDA with SCL high

; Input:  None

; Output: None

; Registers destroyed: R1

; SCL expected low on entry. Return with SCL, SDA high

I2C_Stop:

        clr     SDA

        nop                    ; wait Tf + Tsu:dat, prevent "START"

        mov     R1, #7

        setb    SCL            ; prepare for "STOP"

        djnz    R1, $          ; wait Tr + Tsu:sto (> 5.7us)

        setb    SDA            ; low-to-high SDA with SCL high

        ret

PUBLIC    I2C_OUTB

; bit I2C_OUTB (data BYTE b);

; Shift out a byte to the device, most significant bit first.

;     Read ACK or NAK from the device.

; Input:  R4 - Byte to be shifted out

; Output: Carry flag - Clear if there is not acknowledge

; Registers destroyed: A, PSW, R1, R4

; SCL expected low on entry. Return with SCL low

I2C_OUTB:

        setb    C              ; CY = 1, get ACK bit

        mov     A, R4          ; byte to be shifted in A

        sjmp    I2C_Shift

PUBLIC    I2C_INB

; BYTE I2C_INB (data BYTE SendACK);

; Shift in a byte from the device, most significant bit first.

;     Send ACK or NAK to the device.

; Input:  R4 - 0 - Send NAK to device

;              else - Send ACK to device

; Output: R4 - Received data byte from device

; Registers destroyed: A, PSW, R1

; SCL expected low on entry. Return with SCL low

I2C_INB:

        mov     A, R4

        add     A, #0FFh       ; move ACK bit into CY

        cpl     C

        mov     A, #0FFh       ; SDA high

I2C_Shift:

        mov     R1, #9         ; bit counter, 8 bits + ACK

L_Next_Bit:

        rlc     A              ; move bit7 into CY

        mov     SDA, C         ; output bit

        mov     R4, #2

        djnz    R4, $          ; wait Tr + Tsu:dat + more (3us)

        setb    SCL            ; raise clock

        mov     R4, #4

        djnz    R4, $          ; wait Tr + Thigh (5us)

        mov     C, SDA         ; input bit

        clr     SCL            ; drop clock

        djnz    R1, L_Next_Bit ; now wait Tf + Tlow (> 5us)

        cpl     C              ; ACK bit

        mov     R4, A

        ret

        END



Example of .c routines for interfacing DS1307, block Read/Write functions



bit RTCWriteBlock (data BYTE Addr, data BYTE data *p, data BYTE Count)

{

    bit    Result;

    Result = FALSE;

    I2C_Start ();

    if (I2C_OUTB (0xD0))                            // write

    {

        if (I2C_OUTB (Addr))                        // addr

        {

            Result = TRUE;

            for (; Count; Count--)

            {

                if (!I2C_OUTB (*p++))

                {

                    Result = FALSE;

                    break;

                }

            }

        }

    }

    I2C_Stop ();

    return Result;

}

bit RTCReadBlock (data BYTE Addr, data BYTE data *p, data BYTE Count)

{

    bit    Result;

    Result = FALSE;

    I2C_Start ();

    if (I2C_OUTB (0xD0))                            // write

    {

        if (I2C_OUTB (Addr))                        // addr

        {

            Result = TRUE;

            if (Count)

            {

                I2C_Start ();

                if (Result = I2C_OUTB (0xD1))        // read

                {

                    while (Count)

                    {

                        Count--;

                        *p++ = I2C_INB (Count);

                    }

                }

            }

        }

    }

    I2C_Stop ();

    return Result;

}